FIELD OF THE INVENTION
The invention relates to a circuit configuration with a device for generating digital signals.
As compared with the processing of analog signals, digital signal processing is advantageous in that the signals to be processed, for example binary signals, have a considerably greater signal-to-noise ratio. Even small errors can irreversibly falsify an analog signal. Digital signals are also subject to various kinds of faults, for example noise or superimposed voltage peaks. The degree of these faults depends as a rule on the type and scope of the digital processing. In a series of signal processing stages, faults can accumulate in such a way that even in the case of binary signals the actual signal can no longer be unambiguously determined. At certain points of the signal processing system, for example at the inputs of a logic module, the digital signals are fed to devices for generating digital signals, for example signal amplifiers. These devices, which are also known in digital technology under the designation of receivers or signal regenerators, serve to regenerate the levels of the digital signals. For this purpose, the voltage levels of the individual signals are generally raised or lowered to the agreed setpoint value, provided that the signals lie within a tolerance range and can be assigned to a specific signal value. Which tolerance range is to be used here depends on the standard that has been selected for switching to the signal processing system.
The multiplicity of available logic standards includes, by way of example, the following two:
The LVTTL standard (LVTTL=Low Voltage Transistor/Transistor Logic) provides the voltage levels 0.8 V and 2.0 V for representing the binary states "low" and "high". PA0 In the SSTL standard, the signal value "high" is expressed by increasing the signal by 0.4V with respect to a reference voltage, and the signal value "low" is expressed by reducing the signal by 0.4V with respect to the reference voltage. PA0 a voltage terminal connected to the device for feeding an external reference voltage to the device; PA0 a voltage generator for generating an internal reference voltage and a switch connected between the voltage generator and the device; PA0 a level converter connected to the switch, the level converter outputting a switching signal for switching the switch raised to a level above a switching threshold of the switch; PA0 the level converter having a pair of mutually cross-coupled transistors each having a channel side, and coupling transistors each having a control terminal connected to a first supply potential, the coupling transistors capacitively coupling the cross-coupled transistors on the channel side to the first supply potential.
However, the signal regenerators do not just adapt the binary signal values lying in a tolerance range to these voltage levels. At the same time, when there is a change from one signal value to another, for example "low" to "high", they ensure that the changeover of the signal levels is as rapid as possible. Ideally, the edges of a voltage signal of the binary values which is plotted against time are as steep as possible. Signal regenerators are used wherever digital values have to be evaluated and used in a flexible way. They are also used, for example, in memories for freshening up the address control signals, RAS and CAS, enable signals and the like.
It is not readily possible to use a signal regenerator when there are various logic standards. Signal regenerators can also be used in semiconductor chips which are compatible, for example, with two logic standards. Then, in each case, one signal regenerator has to be provided for each standard. The expenditure, of course, is considerable. Concurrently, the number of connections on the chip increases, which then increases the risk that the internal voltages on the chip affect one another.
German patent DE 33 47 484 C2 discloses a circuit configuration which has the purpose of adapting input signals to a logic signal level for use in logic circuits and process data circuits, and which has a comparator with a positive and a negative input. The input signals are supplied into the circuit by an external input terminal.
Japanese patent application JP 1-319322 A in: Patent Abstracts of Japan, Section E. Vol. 14 (1990) No. 125 (E-900) describes a circuit for converting levels with an operational amplifier which can be connected via a circuit configuration either to an input terminal or to ground. A reference voltage is fed via the non-inverting input of the operational amplifier.